The invention relates to a logic circuit with differential cascode voltage logic.
A logic circuit of this type is reproduced, for example, in the publication by T. Meng et al. entitled "Design of Clock-Free Asynchronous Systems for Real-Time Signal Processing" in the Digest of Technical Papers, pages 2532 to 2535 for the conference IEEE ICCAD 89. This circuit has a logic circuit with two logic blocks which are formed in each instance of n-channel transistors and in which circuit in each instance one part of a logic block is coupled back via an invertor with the gate of a precharging transistor connected to this logic block, in order in each instance to assure the output voltage of the logic blocks on a steady basis until such time as valid data cause a potential change at the output of the logic circuit.
The European Patent Application bearing the publication number 0,147,598 A1 discloses furthermore a system with differential cascode voltage switching logic, in which system a first logic block and a second logic block each have a switch, the switch of the first logic block always being closed when the switch of the second logic plug is open and vice versa, and the switch of the second logic plug being driven in a manner complementary to the switch of the first logic block.